A Selectively Accessing TLB for High Performance and Lower Power Consumption

This paper presents a structure of TLB (translation lookaside buffer) for low power consumption but high performance. The propsed TLB is constructed as a combination of one block buffer and two-way banked TLBs. The processor can access the block buffer or one of two banked TLBs selectively. This feature is quite different from that used in the traditional block buffering technique. Simulation results show its effectiveness in terms of power consumption and Energy*Delay product. The proposed TLB can reduce power consumptions by about 40%, 10%, 23%, and 23%, compared with a FA (fully associative)-TLB, a micro-TLB, a victim-TLB, and a banked-TLB respectively. Also the proposed TLB can reduce Energy*Delay products by about 38%, 28%, 21%, and 21%, compared with a FA-TLB, a micro-TLB, a victim-TLB, and a banked-TLB respectively. Therefore the proposed TLB can achieve low power consumption and high performance with a simple architecture.